Integrated circuits (ICs) include many devices and circuit members that are formed on a single semiconductor wafer. The current trends in IC technology are towards faster and more powerful circuits. However, as more complex ICs such as microprocessors having high operating frequency ranges are manufactured, various speed related problems are becoming increasingly challenging. This is especially true when ICs having different functions are used to create electronic systems, for example computing systems including processor and memory ICs, where different ICs are electrically connected by a global interconnect network. However, as the global interconnects become longer and more numerous in the electronic systems, RC delay and power consumption as well as low system performance are becoming limiting factors.
One proposed solution to this problem is three dimensional (3-D) integration or packaging technology, where 3-D integration refers to the vertical stacking of multiple dies or chips including ICs within a package. In 3-D integration technology, multiple dies are electrically connected using vertical connectors or 3-D conductive structures which may have depths as well as widths or diameters as large as about 100 micrometers or greater. 3-D conductive structures filling 3-D vias extend through one or more of the wafers and are aligned when the wafers are stacked to provide electrical communication among the ICs in the stacked wafers. 3-D integration may result in reductions of size and weight of the IC package, reduction in power consumption, and increase in performance and reliability.
In general, to fabricate the 3-D interconnects, initially deep vias or deep features are formed in the wafers, which are subsequently filled with a conductive material, typically a metal such as copper for its low electrical resistivity and electromigration characteristics. Electroplating is one of the preferred methods to fill deep vias. There are several 3-D integration techniques. One particular technique focuses on thinning the wafers after filling the via holes.
FIGS. 1A-1H illustrate an exemplary method of forming an IC device 100 using a 3-D integration technique involving thinning wafers after filling via holes. First, a wafer or die 110 including substrate-level IC elements 111 (e.g., transistors, capacitors, resistors, etc.) is provided as shown in FIG. 1A. The front surface 110a of the wafer 110 is then coated with an insulating layer, such as SiO2 film 112. Then, a deep via 113 is formed or drilled, e.g., by masking and etching or applying laser drilling as shown in FIG. 1B. In the illustrated example, although only one via 113 is shown for the sake of clarity, it will be appreciated that multiple vias can be formed in the wafer 110.
A dielectric, such as a CVD SiO2 oxide layer may be coated on the wafer surface and inside the via 113 for the purpose of insulating the via metal such as copper from the bulk silicon and also to minimize the smear of metal during the back-surface thinning process of the wafer 110. The dielectric coated deep via 113 is then lined with a barrier layer such as a Ta/TaN layer and a copper seed layer, before filling copper into the deep via 113 using an electrochemical deposition process. In FIG. 1C, although only a single layer 114 is shown to be on the wafer surface and inside the via 113 for the sake of clarity, it will be understood that the lining layer 114 can represent all three of the dielectic layer, the barrier layer, and the copper seed layer.
Then, the via 113 is overfilled with copper 115 using a conventional electrodeposition process. As is well known, as a downside, conventional electrodeposition processes form a thick overburden layer 116 on the surface of the wafer 110, over the via 113 that is filled, as shown in FIG. 1D, when the filling of the via 113 is completed. This unwanted copper layer on the surface of the wafer 100, often referred to as overburden 116, is then planarized using, for example, a chemical mechanical polishing (CMP) process as shown in FIG. 1E to produce a copper plug 115a . Subsequently, metallization layers 117 are formed and patterned to interconnect the substrate-level IC elements 111 to the copper plug 115a formed in the via 113, as shown in FIG. 1F.
In order to expose the copper plug 115a embedded in the wafer 110, the back surface 110b of the wafer 110 is thinned down to reveal the conductive structure or plug 115a from the back surface 110b of the silicon wafer 110, as shown in FIG. 1G. Wafers made in this manner are then diced and the individual dies 110, 120, 130 are aligned and stacked one top of one another, as shown in FIG. 1H, to complete the 3-D IC device 100. Alternatively, stacking can be conducted at the wafer level.
In the illustrated method, the 3D via and copper plug are formed after forming the substrate-level IC elements and before forming the metallization layers. In other examples, the 3D via and copper plug can be formed before forming the substrate-level IC elements in the wafer or after forming the metallization layers. The sequence of forming the foregoing layers or structures can vary widely depending on the fabrication schemes.
Currently, there are technical challenges in 3-D integration, involving, for example, wafer handling, deep via hole formation, barrier and seed layer deposition, plating, and the subsequent planarization processes.
Fabricating such relatively large 3-D conductive structures with present day electroplating technology has difficulties, although the same technology is successfully applied to fill shallow interlevel via holes. As mentioned above, with the current electroplating technology, to adequately fill such deep vias, it is often necessary to deposit relatively thick layers of metal over the surface of the wafer. This in turn requires the use of a subsequent planarization processes to remove the excess metal from the wafer surface, which process also levels the wafer surface for the subsequent manufacturing step. Such planarization processes typically include chemical mechanical planarization (CMP) processes. The very thick metal not only reduces the throughput of the electrochemical deposition (ECD) tool , but also reduces the throughput of the CMP tool, thus increasing the cost of the fabrication. Besides, it is difficult to deposit a continuous barrier and seed layers in these deep vias, which creates a reliability problem for the 3-D interconnect.
Therefore, to this end, there is a need for alternative methods to form defect-free 3-D conductive structures to electrically connect substrates to one another in a substrate stack.